Volatile memories include random access memory (RAM), which can be further divided into two sub-categories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they will lose the information they store when they are not powered. On the other hand, non-volatile memories can keep data stored on them even when not powered.
SRAM cells may comprise different numbers of transistors. According to the total number of transistors in an SRAM cell, the SRAM cell may be referred to as a six-transistor (6-T) SRAM, an eight-transistor (8-T) SRAM, and the like. SRAM cells are arranged in rows and columns. An SRAM cell is selected during either a READ operation or a WRITE operation by selecting its row and column.
Each column of SRAM cells is connected to both a bit-line (BL) and the inverse of BL (BLB). A data latch of each SRAM cell is used to store a single bit. Both BL and BLB are can be used to control the operation of reading a bit from or writing a bit into the SRAM cell. One storage node of the data latch is discharged by BL to “0” and then it flips the other storage node. The BLB's charging is minor to the WRITE operation. Negative bit lines (NLB) can include write-assist circuitry that limits the design or configurability of a particular design. Despite the limiting nature of the write operation, it is critical that input data being written to constituent memory cells (or bit cells) be presented to the memory cells under conditions that ensure proper execution of write operation. Write assist circuitry helps the write operation complete under some circumstances, such as when the power supply level (unit: volt) is low. Many circumstances exacerbate the problem. For example, when the power supply becomes lower or the bitcell's variation becomes worse.